general description the max3971a is a compact 10.7gbps limiting amplifier.it accepts signals over a wide range of input voltage levels and provides constant-level output voltages with con- trolled edge speeds. it functions as a data quantizer with a 240mv p-p differential cml output signal with a 100 dif- ferential termination. the max3971a has a disable func-tion that allows the outputs to be squelched if required by the application. the max3971a is designed to work with the max3970 transimpedance amplifier (tia). the limiting amplifier operates on a single +3.3v supply and functions over a 0 c to +85 c temperature range. the max3971a is offered in die form and in a compact4mm 4mm 20-pin qfn and thin qfn package. applications vsr oc-192 receivers10gbps ethernet optical receivers 10gbps fibre channel receivers features ? single +3.3v power supply ? 2mv p-p input sensitivity ? 1.8ps typical deterministic jitter (v in = 800mv p-p ) ? dice and 4mm 4mm qfn or thin qfn package available ? output disable feature max3971a +3.3v, 10.7gbps limiting amplifier ___________________________________________________ _____________ maxim integrated products 1 max3971a max3970 tia 100 in+ gndin- gndin+ in- supply filter v cc1 v cc2 v cc3 out+ out- cz- cz+ 0.1 f 0.1 f 0.1 f 0.1 f 0.1 f disable 50 50 +3.3v +3.3v typical application circuit * ep = exposed pad. ** dice are designed to operate over a 0? to +110? junction- temperature (t j ) range, but are tested and guaranteed at t a = +25?. + denotes lead-free package. ordering information par emp range pin-package pkg code MAX3971AUGP 0c to +85c 20 qfn-ep* g2044-4 max3971autp 0c to +85c 20 thin qfn-ep* t2044-3 max3971autp+ 0c to +85c 20 thin qfn-ep* t2044-3 max3971au/d 0c to +85c dice** 19-2391; rev 2; 2/07 for pricing, delivery, and ordering information, please contact maxim/dallas direct! at 1-888-629-4642, or visit maxim? website at www.maxim-ic.com. pin configurations appear at end of data sheet. downloaded from: http:///
max3971a +3.3v, 10.7gbps limiting amplifier 2 __________________________________________________ _____________________________________ absolute maximum ratings supply voltage, v cc1 , v cc2 , v cc3 ......................-0.5v to +5.0 v voltage at in+, in-, disable, cz+, cz-, out+, out- .........................................+0.5v to (v cc + 0.5v) differential voltage between cz+ and cz- ...........................?v differential voltage between in+ and in-...........................?.5v continuous power dissipation (t a = +85?) 20-pin qfn (derate 20mw/? above +85?) .................1.3w operating ambient temperature range .............-40? to +85? storage temperature range .............................-55? to +150? die attach temperature...................................................+400? lead temperature (soldering, 10s) .................................+300? stresses beyond those listed under ?bsolute maximum ratings?may cause permanent damage to the device. these are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. exposure to absolute maximum rating conditions for extended periods may affect device reliability. electrical characteristics (v cc = +3.0v to +3.6v, output load = 50 to v cc , t a = 0? to +85?, unless otherwise noted. all ac parameters are measured with a 2 23 - 1 prbs pattern applied to the input at 10.7gbps. typical values are at v cc = +3.3v, t a = +25?, unless otherwise noted.) parameter symbol conditions min typ max units supply current i cc 50 85 ma small-signal bandwidth bw 10 ghz input sensitivity v in-min (notes 1, 2) 2 5 mv p-p input overload v in-max (note 1) 1200 mv p-p low-frequency cutoff cz = 0.1? (note 1) 60 75 khz 5mv p-p input (notes 1, 3) 5.2 16.0 10mv p-p input (notes 1, 3) 3.5 14.0 800mv p-p input (notes 1, 3) 1.8 7.0 deterministic jitter 1200mv p-p input (notes 1, 3) 1.9 11.0 ps random jitter 20mv p-p < input < 1200mv p-p (notes 1, 4) 0.6 1.1 ps rms transition time t r , t f 20% to 80%, differential output (note 1) 20 30 ps data input impedance single ended 42 50 58 data output-voltage swing differential signal amplitude betweenout+ and out- 190 240 400 mv p-p data output voltage whendisabled differential signal amplitudebetween out+ and out- 0.25 50 mv p-p data output common-modevoltage v cc - 75 mv data output impedance single ended 42 50 58 data output offset whendisable is high 75 200 mv disable input current 30 60 ? disable high voltage v ih 2v disable low voltage v il 0.8 v disable response time 20 ns note 1: guaranteed by design and characterization. note 2: the output signal amplitude at the sensitivity is > .95 ? the amplitude with large input. note 3: deterministic jitter is measured with k28.5 pattern (0011 1110 1011 0000 0101) at 10.7gbps. it is the peak-to-peak devia-tion from the ideal time crossing, measured at the zero-level crossing of the differential output. note 4: for a bit-error rate of 10 -12 , the peak-to-peak random jitter is 14.1 ? the rms random jitter. downloaded from: http:///
max3971a +3.3v, 10.7gbps limiting amplifier _______________________________________________________________________________________ 3 output eye diagram (input signal = 10mv p-p , at 10.7gbps) max3971a toc01 20ps/div 45mv/div 2 23 - 1prbs output eye diagram (input signal = 5mv p-p , at 10.3gbps) max3971a toc02 20ps/div 45mv/div 2 23 - 1prbs output eye diagram (input signal = 1200mv p-p , at 10.3gbps) max3971a toc03 20ps/div 45mv/div 2 23 - 1prbs output eye diagram (input signal = 800mv p-p , at 10.7gbps) max3971a toc04 20ps/div 45mv/div 2 23 - 1prbs output voltage vs. input voltage max3971a toc07 v in (mv p-p ) v out (mv p-p ) 5 4 3 2 1 170 190 210 230 250 270150 06 supply current vs. ambient temperature max3971a toc05 temperature ( c) supply current (ma) 70 60 40 50 20 30 10 42 44 46 48 50 52 54 56 58 6040 08 0 small-signal gain max3971a toc06 frequency (ghz) gain (db) 14 13 11 12 4 5 6 7 8 9 10 2 3 5 10 15 20 25 30 35 40 45 50 0 11 5 max3971a ugp random jitter vs. input amplitude max3971a toc08 input amplitude (mv p-p ) random jitter (ps rms ) 1000 100 10 0.5 1.0 1.5 2.0 2.5 3.0 3.5 0 1 10,000 deterministic jitter vs. input amplitude max39971a toc09 input amplitude (mv p-p ) jitter (ps p-p ) 1000 100 10 1 2 3 4 5 60 1 10,000 10.7gbps, k28.5, v cc = +3v, temp = 85 c typical operating characteristics (v cc = +3.3v, output load = 50 to v cc , t a = +25?, unless otherwise noted.) downloaded from: http:///
max3971a +3.3v, 10.7gbps limiting amplifier 4 __________________________________________________ _____________________________________ typical operating characteristics (continued) (v cc = +3.3v, output load = 50 to v cc , t a = +25?, unless otherwise noted.) deterministic jitter vs. temperature max3971a toc10 ambient temperature ( c) jitter (ps p-p ) 70 60 50 40 30 20 10 1 2 3 4 5 6 70 08 0 v in = 5mv v in = 800mv 10.7gbps with k28.5 input return loss (s11) (v cc = +3.3v) max3971a toc11 frequency (ghz) loss (db) 987654321 -25 -20 -15 -10 -5 0 -30 01 0 max3971a output return loss (s22) (v cc = +3.3v) max3971a toc12 frequency (ghz) loss (db) 98 67 2345 1 -40 -35 -30 -25 -20 -15 -10 -5 0 -45 01 0 max3971a output noise power (input connected to 50 to gnd) max3971a toc13 temperature ( c) noise power (dbm) 70 60 50 40 30 20 10 -19.5 -19.4 -19.3 -19.2 -19.1 -19.0-19.6 08 0 power-supply rejection ratio vs. frequency max3971a toc14 frequency (hz) psrr (db) 10m 1m 100k 35 40 4530 10k 100m psrr = -20log v out / v cc input common-mode rejection ratio vs. frequency max3971a toc15 frequency (hz) cmrr (db) 1g 100m 10m 1m 45 50 55 60 65 7040 100 10g cmrr = -20log(v out /v in ) v in = v in+ = v in- downloaded from: http:///
pin description pin name func tion 1 gndin+ input ground for shielding input signal in+. not connected internally. 2 in+ noninverting input signal 3 in- inverting input signal 4 gndin- input ground for shielding input signal in-. not connected intern ally. 5, 7, 9, 10 n.c. no connection. leave unconnected. 6, 8, 11 gnd ground 12, 15 v cc3 output circuitry power supply 13 out- inverting output of amplifier 14 out+ noninverting output of amplifier 16 disable when disable is connected to v cc or left floating, outputs are disabled. when disable is connected to gnd, outputs are enabled. 17 v cc2 power supply to circuitry other than input and output circuits 18 cz+ filter capacitor for offset correction. connect cz between pin 18 and p in 19. see the deailed descripion section. 19 cz- filter capacitor for offset correction. connect cz between pin 18 and p in 19. see the deailed descripion section. 20 v cc1 input circuitry power supply ep exposed pad. must be soldered to supply ground for proper electric al and thermal operation. max3971a +3.3v, 10.7gbps limiting amplifier _______________________________________________________________________________________ 5 detailed description and applications information figure 1 is a functional diagram of the max3971a limit-ing amplifier. the signal path consists of an input buffer followed by a gain stage and output amplifier. a feed- back loop provides offset correction by driving the average value of the differential output to zero. gain stage and offset correction the limiting amplifier provides approximately 42dbgain. the large gain makes the amplifier susceptible to small dc offsets, which cause deterministic jitter. a low-frequency loop is integrated into the limiting ampli- fier to reduce output offset, typically to less than 2mv. the external capacitor (cz) is required for stability and to set the low-frequency cutoff for the offset correction loop. the time constant of the loop is set by the product of an equivalent 20k on-chip resistor and the value of the off-chip capacitor (cz). for stable operation, theminimum value of cz is 0.01?. to minimize pattern- dependent jitter, cz should be as large as possible. for 10gbps ethernet and sonet applications, the typi- cal value of cz is 0.1?. keep cz close to the package to reduce parasitic inductance. cml input circuit the input buffer is designed to accept cml input sig-nals such as the output from the max3970 transimped- ance amplifier. an equivalent circuit for the input is shown in figure 2. for lowest deterministic jitter in all operating conditions, ac-coupling capacitors are rec- ommended on the input. max3971a cz- cz+ lowpass filter cz offset correction amp input amplifier gain 42db output amplifier out+ out- in+ gndin+gndin- in- disable 100 figure 1. functional diagram downloaded from: http:///
cml output circuit an equivalent circuit for the output network is shown infigure 3. it consists of a pair of 50 resistors connect- ed to v cc driven by the collectors of an output differen- tial transistor pair (q1 and q2). the differential outputsignals are clamped by transistors q3 and q4 when the disable input is high. disable function a logic signal can be applied to the disable pin tosquelch the output signal. when the output is disabled, an offset is added to the output, preventing the follow- ing stage from oscillating, if dc-coupled. see figure 4 for the input stage of the disable function. max3971a +3.3v, 10.7gbps limiting amplifier 6 __________________________________________________ _____________________________________ +3.3v 100k disable 20 a figure 4. ttl input stage v cc1 50 50 in+ gndin+ gndin- in- esd structures figure 2. cml input equivalent circuit v cc3 50 50 q1 q2 q3 q4 out+out- disable data esd structures figure 3. cml output equivalent circuit +3.3v max3971a v cc1 v cc2 v cc3 0.001 f 0.001 f 0.001 f l supply filter figure 5. power-supply filter downloaded from: http:///
max3971a +3.3v, 10.7gbps limiting amplifier ___________________________________________________ ____________________________________ 7 layout considerations circuit board layout and design can significantly affectthe performance of the max3971a. use good high-fre- quency techniques, including fixed-impedance trans- mission lines for the high-frequency data signal. use a multilayer board with solid ground plane. minimize the inductance between the max3971a and the ground plane. the max3971a uses three power-supply pins (v cc1 , v cc2 , and v cc3 ). the input circuitry of the max3971a is supplied by v cc1 . the output drivers have a separate supply (v cc3 ), which usually has large pulsing currents. all other circuitry is powered by v cc2 . it is possible to simply connect the three pins together. however, using asupply filter ensures better isolation of the input circuitry. for optimal isolation, figure 5 shows a possible supply- filtering circuit. element l, a ferrite bead, provides isola-tion between a noisy v cc3 and a sensitive v cc1 . chip information transistor count: 324process: sige bipolar substrate: electrically isolated 19 cz- 20 v cc1 18 cz+ 17 v cc2 16 disable 9 n.c. 10 n.c. 8 gnd 7 n.c. 6 gnd 4 gndin- 5 n.c. 3 in- 2 in+ 1 gndin+ 14 out+ 15 v cc3 13 out- 12 v cc3 11 gnd max3971a qfn 4mm x 4mm the exposed pad must be soldered to gnd forproper thermal and electrical performance. 45 3 2 1211 13 n.c.n.c. 14 gnd cz-v cc2 disable v cc1 6 7 in- 910 20 19 17 16 gndin- n.c. out+out- v cc3 gnd max3971a gnd cz+ 8 18 in+ 1 15 v cc3 gndin+ thin qfn 4mm x 4mm top view n.c. the exposed pad must be connected to ground forproper thermal and electrical performance. pin configurations downloaded from: http:///
max3971a +3.3v, 10.7gbps limiting amplifier 8 __________________________________________________ _____________________________________ gndin+ in+ in- gndin- nc v cc3 out+ out- v cc3 gnd gnd n.c. gnd n.c. n.c. v cc1 cz- cz+ v cc2 disable 0.052" (1.33mm) 0.042" (1.10mm) (0, 0) chip topography downloaded from: http:///
max3971a +3.3v, 10.7gbps limiting amplifier maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a maxim product. no circuit patent licenses are implied. maxim reserves the right to change the circuitry and specifications without notice at any time. maxim integrated products, 120 san gabriel drive, sunnyvale, ca 94086 408-737-7600 _____________________ 9 2007 maxim integrated products is a registered trademark of maxim integrated products. max3971a pad number x dimension (?) y dimension (?) 1 16 554 2 26 418 3 26 287 4 16 151 51 63 9 6 191 -92 7 303 -92 8 415 -92 9 527 -92 10 639 -92 11 978 67 12 978 179 13 974 315 14 974 446 15 978 582 16 825 647 17 713 647 18 601 647 19 489 647 20 377 647 pad dimensions: passivation opening: 94.4? ? 94.4? metal: 102.4? ? 102.4? all measurements specify the lower left corner of the pad. refer to application note h fan-08.0: understanding bonding coordinates and physical die size . chip topography (continued) package information for the latest package outline information, go to www.maxim-ic.com/packages . revision history rev 0; 4/02: initial data sheet release. rev 1; 5/03: added package code to ordering information and deleted ep references from ordering information (page 1); updated package drawing (page 10). rev 2; 2/07: added thin qfn package (pages 1 and 7); removed package drawing. downloaded from: http:///
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